AMD cpu has roughly about 20 stage pipeline and P4 has roughly about 30 stage pipeline ... To explain more, just imagine between 2 stairs, one has 30 steps and the other has 20 steps, and both stairs are 10ft high. That also explain why intel P4 is capable of running at much higher frequency than amd but finish the task at roughly the same time at the same rating. Each of the application in the PC when start executing require a complete pipeline flush (or clear the stair of people walking up). When only one app is running you can have instructions continuously in the pipeline (or stair is full of people walking up one after another). From this, one can see that when you switch app, intel P4 has to clear 30 stages while amd only have to clear 20. Hence explain the sluggish some people have with non HT P4 cpu. HT is like having another little guy (roughly 5-10 stages) that using part of the pipeline on an entirely different app smartly when there is a hole available. In another word, one smart module monitor the pipeline and if there is a gap larger than 5 pipeline stages, it will try to insert instructions from a different app. When switching between apps it also does not clear the entire pipeline, if it finds another app is running in the pipeline, but rather only clear the stages that it need at the moment. It can be done with P4 but not AMD because on a 20stages cpu, you can hardly find 5 stages empty when running one app. Intel did this to fight it's own problem when they make P4 family cpu and experience sluggish in multitasking due to extra long pipeline. Right now, Intel is trying to abandon long pipeline cpu and going back to extra short pipeline because they have hit the frequency wall on sillicon. You can see this in the new dothan chip, and I suspect the pentium M has even less than 20 stage pipeline. So whether you like HT or not it is going away because you simply can not implement HT in a short pipeline cpu. So again, HT would only improve extra long pipeline cpu. CPU bandwidth and cache: Most new applications (like game) nowaday require a large amount of data flowing through the cpu. You can fight this problem 2 ways: 1. In crease the cpu bandwidth. The good example is AMD is trying to reduce diesize by only using 512K cache and increase FSB to 1000MHzx2 (HTT in socket 939). This has good avantage on game since most new game require a much bigger instructions set sometimes much larger than 1M or 2M. 2. Increase the CPU cache. Intel is doing this on new processors some has 1M cache and some has 2M cache. This has a disavantage if the apps require bigger than 2M instruction set the apps will become sluggish because the cpu is waiting for data. But if the apps has a small footprint that fit in the cpu internal cache the app will run a lot faster than amd since the bandwidth of internal cache is much faster than 2000MHz (close to cpu speed) From the above one can say that why not just implement both high bandwidth and large cache? Or Just get rid of cache altogether and improve the cpu bandwidth to as high as the cpu? This is impossible to do with the current technology since cpu is in the muti GHz range where the bandwidth is only from 800-2000MHz. Or Make the cache 3M, 4M or as large as possible? This is also impossible because the yield will decrease dramatically with large diesize. Not to mention the cost per cpu will increase dramatically even if the yield is high. Now whether you like HT or HTT also depends on the type of apps you use and the amount of cache you have in the cpu as well. As for me (admin for a chip design company), most apps I use are as large as 1-16GB footprint so we choose dual or quad opteron as our PC of choice as dual Xeon performs poorly. In the future, if pentium M is better for my applications, I would certainly choose it over AMD. :lele:
cha viết tiếng việt đi.. móa dân trong này là dziẹtnamese mà cha.. đại đa số tiếng mẽo biết họ nhưng họ không biết tiếng mẽo hehhehe
hehe bài này nguquen viết ở forum khác xài tiếng mẽo mờ ... Tui hông biết dịch ra đâu cha.. Cha hiểu làm ơn dịch dùm đê
đó cũng lý do tại sao Intel lại delay project 4ghz ? Intel đợi IBM ra loại sillicon mới chăng ?
hay lắm đại ca nguquen :good: vay thi` anh em IT tập đọc tiếng Anh cho quen, chứ bảo dịch ra tiếng Viet thi` cũng hơi khó khi nguoi dich đòi hỏi phai thong 2 thứ tieng, trong khi danh từ kỷ thuat IT tiếng Viết khong phai là dễ .
